The present invention relates to a nonvolatile semiconductor memory device and to a method for fabricating the same. In particular, it relates to a nonvolatile semiconductor memory device having memory elements and peripheral circuits for inputting and outputting data to and from the memory elements formed on a single semiconductor substrate and to a method for fabricating the same.
At present, flash EEPROM (Electrically Erasable Programmable ROM) devices (hereinafter referred to as FEEPROM devices) have been used widely in electronic equipment as nonvolatile semiconductor memory devices which allow for electrical write and erase operations. The structures of memory cells in a nonvolatile semiconductor memory element can be divided roughly into two types, which are a stacked-gate type having a multilayer electrode structure composed of a floating gate electrode and a control gate electrode stacked on a semiconductor substrate and a split-gate type having an electrode structure composed of a floating gate electrode and a control gate electrode each opposed to a channel region in a semiconductor substrate.
The memory cells of the split-gate type are larger in size than those of the stacked-gate type because of the floating gate electrode and the control gate electrode disposed adjacent to each other on the semiconductor substrate. In addition, the floating gate electrode and the control gate electrode adjacent to each other are formed by individual lithographic steps, which requires a margin for the alignment of respective masks used to form the floating gate electrode and the control gate electrode. With the margin, the memory cells tend to be further increased in size.
FIGS. 58A to 58H show the cross-sectional structures of a conventional split-gate FEEPROM device in the individual process steps.
First, as shown in FIG. 58A, an insulating film 202 is formed on a semiconductor substrate 201 composed of silicon. Then, control gate electrodes 203 are formed selectively on the insulating film 202.
Next, as shown in FIG. 58B, the portion of the insulating film 202 on the region of the semiconductor substrate 201 to be formed with drains is removed therefrom by wet etching by using a first mask pattern 251 having an opening corresponding to the drain formation region and the gate electrodes 203 as a mask. Then, boron (B) ions at a relatively low dose are implanted into the semiconductor substrate 201 such that a lightly doped p-type region 204 is formed in the drain formation region.
Next, as shown in FIG. 58C, a silicon dioxide film having a thickness of about 100 nm and doped with boron (B) and phosphorus (P) (BPSG (Boron Phosphorus Silicate Glass)) film is deposited over the entire surface of the semiconductor substrate 201. The deposited BPSG film is etched back by anisotropic etching to form sidewalls 205 composed of the BPSG film on the both side surfaces of each of the control gate electrodes 203.
Next, as shown in FIG. 58D, dry etching is performed with respect to the semiconductor substrate 201 by using a second mask pattern 252 having an opening corresponding to the drain formation region of the semiconductor substrate 201, the gate electrode 203, and the side walls 205 as a mask, thereby forming a recessed portion 201a having a stepped portion composed of the portion of the semiconductor substrate 201 underlying the sidewall 205 as the upper stage and the drain formation region as the lower stage.
Next, as shown in FIG. 58E, arsenic (As) ions at a relatively low dose are implanted into the semiconductor substrate 201 by using the second mask pattern 252, the gate electrode 203, and the sidewall 205 as a mask, whereby an LDD region 206 as a lightly doped n-type region is formed in the drain formation region.
Next, as shown in FIG. 58F, the sidewalls 205 are removed by using vapor-phase hydrofluoric acid and the semiconductor substrate 201 is thermally oxidized in an oxygen atmosphere at about 850xc2x0 C., whereby a thermal oxide film 207 with a thickness of about 9 nm is formed over the entire surface of the semiconductor substrate 201 including the gate electrodes 203. The portion of the thermal oxide film 207 overlying the drain formation region serves as a tunnel oxide film for each of floating gate electrodes.
Next, a polysilicon film doped with phosphorus (P) is deposited over the entire surface of the semiconductor substrate 201 and etched back to form sidewalls composed of the polysilicon film on the both side surfaces of the control gate electrodes 203. Then, as shown in FIG. 58G, the sidewall closer to a region to be formed with sources is removed, while the sidewall closer to the drain formation region of the semiconductor substrate 201 is divided into parts corresponding to individual memory cells on a one-by-one basis, thereby forming floating gate electrodes 208 composed of the polysilicon film in the drain formation region.
Next, as shown in FIG. 58H, arsenic (As) ions are implanted into the semiconductor substrate 201 by using the gate electrodes 203 and the floating gate electrodes 208 as a mask such that source and drain regions 209 and 210 are formed in the source formation region and in the drain formation region, respectively, whereby memory cells in the FEEPROM device are completed.
Since the floating gate electrodes 208 each opposed to the control gate electrode 203 via the thermal oxide film 208 serving as a capacitance insulating film is thus formed by self alignment relative to the control gate electrode 203, it is sufficient to perform only one lithographic step for forming the gate electrode 203 and a displacement does not occur between the control gate electrode 203 and the floating gate electrode 208 during the alignment thereof.
In a typical method for fabricating the conventional FEEPROM device, however, the floating gate electrode 208, the thermal oxide film 207, and the control gate electrode 203 covered with the thermal oxide film 207 which are shown in FIG. 58G are mostly composed of polysilicon, a silicon dioxide, and polysilicon, respectively. This causes the problem that, if the floating gate electrode 208 is to be formed selectively by etching, the control gate electrode 203 composed of the same material composing the floating gate electrode 208 may be damaged unless the etching speed is controlled with high precision.
Although the thermal oxide film 207 serving as the capacitance insulating film between the control gate electrode 203 and the floating gate electrode 208 and serving as the tunnel insulating film between the floating gate electrode 208 and the semiconductor substrate 201 is formed in the single step illustrated in FIG. 58F, if the tunnel film is formed after the formation of the capacitance insulating film, the interface between the control gate electrode 203 and the capacitance insulating film is oxidized or a bird""s beak occurs at the interface, which causes the problem that the thickness of the capacitance insulating film is increased locally and the capacitance insulating film does not have a specified capacitance value.
In the split-gate or stacked-gate FEEPROM device, if not only the memory cells but also other elements, particularly active elements such as MOS transistors each of which controls carriers implanted from the source region by using the gate electrode, are formed on a single semiconductor substrate, it is typical to simultaneously form the control gate electrodes of the FEEPROM device and the gate electrodes of the MOS transistors.
In terms of reducing the number of fabrication process steps, the conventional fabrication method is desirable since it simultaneously forms the control gate electrodes of the memory cells and the gate electrodes of the MOS transistors contained in, e.g., peripheral circuits or the like for controlling the memory cells. However, the memory cells of a FEEPROM device are larger in element size than MOS transistors whether the FEEPROM device is of the split-gate type or stacked-gate type. If the memory cells and the MOS transistors are formed simultaneously, each of the memory cells and the MOS transistors cannot be formed as an element with an optimum structure. If the diffusion region of each of the memory cells and the MOS transistors is provided with an LDD (Lightly Doped Drain) structure, the concentration of a diffused impurity differs from one region to another so that it is difficult to provide an optimum structure by forming each of the elements simultaneously.
If a method for fabricating a semiconductor device composed only of existing MOS transistors has been established, it is not easy to form, on a single substrate, the semiconductor device containing the existing MOS transistors and the memory cells of a FEEPROM device as shown in FIGS. 58.
If a method for fabricating a semiconductor device by forming, on a single substrate, other memory cells different in structure from those shown in FIGS. 58 and MOS transistors has been established, it is also not easy to form the other memory cells as a replacement for the memory cells shown in FIG. 58. This is because the fabrication process for the memory cells of the FEEPROM, in particular, adversely affects the fabrication of the MOS transistors.
Since the method for fabricating the split-gate FEEPROM device shown in FIGS. 58 forms the floating gate electrodes 208 after forming the control gate electrodes 203 on the semiconductor substrate 201, the floating gate electrodes 208 can be formed by self alignment relative to the control gate electrode 203 so that the memory cells are reduced in size.
As a method for fabricating such memory cells and MOS transistors on a single semiconductor substrate, the following process steps can be considered.
First, the gate electrodes of the MOS transistors to be formed in the other regions of the semiconductor substrate 201 are formed by simultaneous patterning during the formation of the control gate electrodes 203 shown in FIG. 58A.
Next, as shown in FIGS. 58B to 58G, the process steps for fabricating the memory cells are performed. If the implant conditions for the LDD region 206 coincide with the implant conditions for the LDD region of each of the MOS transistors, the impurity is implanted simultaneously into the LDD region of the MOS transistor.
Next, as shown in FIG. 58H, the source and drain regions of each of the MOS transistors are formed simultaneously with the formation of the source and drain regions 209 and 210 of each of the memory cells.
Thereafter, a specified interlayer insulating film and a specified multilayer interconnect are formed by a normal fabrication process, whereby a semiconductor device composed of the memory cells and the MOS transistors formed on the single semiconductor substrate 201 is implemented.
In accordance with the fabrication method, however, the thermal oxide film 207 serving as the tunnel oxide film between the semiconductor substrate 201 and each of the floating gate electrodes 208 is formed also on the upper and side surfaces of the gate electrode of each of the MOS transistors, which causes the necessity to remove the portion of the thermal oxide film 207 covering the gate electrode.
It is to be noted that the gate electrode of each of the MOS transistors is typically composed of polysilicon and each of the gate oxide film and the film protecting the source and drain regions of the MOS transistor is a silicon dioxide film. To selectively remove the thermal oxide film 207 from the gate electrode composed of polysilicon, therefore, the etching speed for the MOS transistor should also be controlled with high precision, which renders the fabrication of the semiconductor device more difficult.
If the thermal oxide film 207 of the gate electrode of each of the MOS transistors is removed by wet etching using hydrofluoric acid, e.g., the thermal oxide film 207 covering the upper and side surfaces of each of the control gate electrodes in the memory cell portion is also etched. If etching proceeds to the control gate electrode 203, the performance of the control gate electrode 203 may also deteriorate.
In addition, etching may also proceed to the LDD and channel regions of each of the MOS transistors formed in the previous steps after the removal of the thermal oxide film 207. This reduces the depth of a junction in the channel region and increases resistance in the channel region, resulting in a reduced amount of current between the source and drain. As a result, the driving ability of the MOS transistor is lowered.
In the conventional semiconductor device in which the memory cells and the MOS transistors are formed on the single semiconductor substrate, if only the memory cell portion is composed of the split-gate memory cells shown in FIGS. 58, the MOS transistors are influenced by thermal hysteresis, which has not been observed previously. This causes the necessity to change the design of the entire semiconductor device. Since the thermal oxide film 207 is formed after the formation of the LDD region 206, e.g., an implant profile in the LDD region of each of the MOS transistors changes to change the operating characteristics of the MOS transistor, which causes the necessity to change process conditions including an amount of ions to be implanted in the LDD region.
In view of the foregoing problems, it is therefore a first object of the present invention to ensures the formation of memory cells in a split-gate nonvolatile semiconductor memory device. A second object of the present invention is to allow easy replacement of existing memory cells with memory cells according to the present invention by utilizing a fabrication process for a semiconductor memory device in which the existing memory cells and MOS transistors are formed on a single semiconductor substrate and prevent the memory cells according to the present invention from affecting the operating characteristics of the MOS transistors.
To attain the first object, the present invention provides a memory cell having a protective insulating film formed on a side surface of a control gate electrode to protect the control gate electrode from etching.
To attain the second object, the present invention provides a method for fabricating a nonvolatile semiconductor memory device in which the memory cell for attaining the first object of the present invention is formed first and then a transistor is formed, thereby preventing the step of forming the memory cell from affecting the operating characteristics of the transistor.
Specifically, a first nonvolatile semiconductor memory device for attaining the first object of the present invention has a control gate electrode and a floating gate electrode provided on a semiconductor substrate to have their respective side surfaces in opposed relation, the device comprising: a gate insulating film formed on the semiconductor substrate; the control gate electrode formed on the gate insulating film; a protective insulating film deposited on each of the side surfaces of the control gate electrode to protect the control gate electrode during formation of the floating gate electrode; the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode; a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate; a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode; and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.
Since the first nonvolatile semiconductor memory device has the protective insulating film deposited on each of the side surfaces of the control gate electrode to protect the control gate electrode during the formation of the floating gate electrode, the configuration of the control gate electrode is not impaired by etching or the like during the formation of the floating gate electrode. This ensures the formation of a memory cell in the nonvolatile semiconductor memory device.
A second nonvolatile semiconductor memory device for attaining the first object of the present invention has a control gate electrode and a floating gate electrode provided on a semiconductor substrate to have their respective side surfaces in opposed relation, the device comprising: a gate insulating film formed on the semiconductor substrate; the control gate electrode formed on the gate insulating film; a protective insulating film deposited only on that one of the side surfaces of the control gate electrode opposed to the floating gate electrode to protect the control gate electrode during formation of the floating gate electrode; the floating gate electrode opposed to the side surface of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode; a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate; a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode; and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.
Since the second nonvolatile semiconductor memory device has the protective insulating film deposited only on the side surface of the control gate electrode opposed to the floating gate electrode to protect the control gate electrode during the formation of the floating gate electrode, the configuration of the control gate electrode is not impaired during the formation of the floating gate electrode. This ensures the formation of a memory cell in the nonvolatile semiconductor memory device.
A third nonvolatile semiconductor memory device for attaining the first object of the present invention has a control gate electrode and a floating gate electrode provided on a semiconductor substrate to have their respective side surfaces in opposed relation, the device comprising: a gate insulating film formed on the semiconductor substrate; the control gate electrode formed on the gate insulating film; a protective insulating film deposited on that one of the side surfaces of the control gate electrode opposite to the side surface opposed to the floating gate electrode to protect the control gate electrode during formation of the floating gate electrode; a capacitance insulating film formed on the side surface of the control gate electrode opposed to the floating gate electrode; the floating gate electrode opposed to the side surface of the control gate electrode with the capacitance insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode; a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate; a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode; and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.
Since the third nonvolatile semiconductor memory device has the protective insulating film deposited on the side surface of the control gate electrode opposite to the floating gate electrode to protect the control gate electrode during the formation of the floating gate electrode, the configuration of the control gate electrode is not impaired during the formation of the floating gate electrode. This ensures the formation of a memory cell in the nonvolatile semiconductor memory device.
In the third nonvolatile semiconductor memory device, the capacitance insulating film preferably has a uniform thickness.
In each of the first to third nonvolatile semiconductor memory devices, the protective insulating film preferably has a uniform thickness.
In each of the first to third nonvolatile semiconductor memory devices, the gate insulating film preferably has a uniform thickness.
In each of the first to third nonvolatile semiconductor memory devices, the tunnel insulating film preferably has a uniform thickness.
Preferably, each of the first to third nonvolatile semiconductor memory devices further comprises an insulating film formed between the control gate electrode and the protective insulating film.
In each of the first to third nonvolatile semiconductor memory devices, the protective insulating film is preferably a multilayer structure composed of a plurality of stacked insulating films having different compositions.
In each of the first to third nonvolatile semiconductor memory devices, the semiconductor substrate preferably has a stepped portion formed to be covered up with the floating gate electrode.
A first method for fabricating a nonvolatile semiconductor memory device, which is for attaining the first object of the present invention, comprises: a control-gate-electrode forming step of forming a first insulating film on a semiconductor substrate, patterning a conductor film formed on the first insulating film, and thereby forming a control gate electrode from the conductor film; a second-insulating-film depositing step of depositing a second insulating film over the entire surface of the semiconductor substrate including the control gate electrode; a protective-insulating-film depositing step of selectively removing the second insulating film so as to leave a portion of the second insulating film located on each of side surfaces of the control gate electrode and thereby forming, from the second insulating film, a protective insulating film for protecting the control gate electrode; a gate-insulating-film forming step of selectively removing the first insulating film so as to leave a portion of the first insulating film underlying the control gate electrode and thereby forming a gate insulating film from the first insulating film; a tunnel-insulating-film forming step of forming, on the semiconductor substrate, a third insulating film serving as a tunnel insulating film; a floating-gate-electrode forming step of forming by self alignment a floating gate electrode capacitively coupled to one of side surfaces of the control gate electrode with the protective insulating film interposed therebetween and opposed to the semiconductor substrate with the tunnel insulating film interposed therebetween; and a source/drain forming step of implanting an impurity into the semiconductor substrate by using the control gate electrode and the floating gate electrode as a mask and thereby forming a source region and a drain region in the semiconductor substrate.
In accordance with the first method for fabricating a nonvolatile semiconductor memory device, each of the side surfaces of the control gate electrode is covered with the protective insulating film also serving as the capacitance insulating film when the floating gate electrode capacitively coupled to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween and opposed to the semiconductor substrate with the tunnel insulating film interposed therebetween is formed by self alignment. The arrangement prevents damage caused by etching to the control gate electrode and ensures the formation of a memory cell in the nonvolatile semiconductor memory device.
A second method for fabricating a nonvolatile semiconductor memory device, which is for attaining the first object of the present invention, comprises: a control-gate-electrode forming step of forming a first insulating film on a semiconductor substrate, patterning a conductor film formed on the first insulating film, and thereby forming a control gate electrode from the conductor film; a second-insulating-film depositing step of depositing a second insulating film over the entire surface of the semiconductor substrate including the control gate electrode; a sidewall forming step of forming sidewalls over the first insulating film and on portions of the second insulating film located on side surfaces of the control gate electrode; a protective-insulating-film forming step of performing etching with respect to the first and second insulating films by using the sidewalls and the control gate electrode as a mask and thereby forming, from the second insulating film, a protective insulating film for protecting the control gate electrode on each of the side surfaces of the control gate electrode, while forming, from the first insulating film, a gate insulating film under the control gate electrode; a tunnel-insulating-film forming step of removing the sidewalls and then forming, in a region in which the semiconductor substrate is exposed, a third insulating film serving as a tunnel insulating film; a floating-gate-electrode forming step of forming by self alignment a floating gate electrode capacitively coupled to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween and opposed to the semiconductor substrate with the tunnel insulating film interposed therebetween; and a source/drain forming step of implanting an impurity into the semiconductor substrate by using the control gate electrode and the floating gate electrode as a mask and thereby forming a source region and a drain region in the semiconductor substrate.
In accordance with the second method for fabricating a nonvolatile semiconductor memory device, each of the side surfaces of the control gate electrode is covered with the protective insulating film when the floating gate electrode capacitively coupled to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween and opposed to the semiconductor substrate with the tunnel insulating film interposed therebetween is formed by self alignment. The arrangement prevents damage caused by etching to the control gate electrode and ensures the formation of a memory cell in the nonvolatile semiconductor memory device.
In the second method for fabricating a nonvolatile semiconductor memory device, the tunnel-insulating-film forming step preferably includes removing the sidewalls and then selectively removing respective portions of the protective insulating film covered with bottom surfaces of the sidewalls. The arrangement suppresses the trapping of electrons or holes in the portions of the protective insulating film covered with the bottom surfaces of the sidewalls and thereby suppresses the degradation of a memory element due to an increase in the number of write or erase operations performed with respect to the memory clement.
In this case, the tunnel-insulating-film forming step preferably includes the step of selectively removing the respective portions of the protective insulating film covered with the bottom surfaces of the sidewalls and then selectively removing respective portions of the gate insulating film covered with the bottom surfaces of the sidewalls. The arrangement suppresses the trapping of electrons or holes in the portions of the gate insulating film covered with the bottom surfaces of the sidewalls and thereby reduces the degradation of the write and erase characteristics of a memory element.
Preferably, the second method for fabricating a nonvolatile semiconductor memory device further comprises, between the protective-insulating-film forming step and the tunnel-insulating-film forming step, the step of: performing etching with respect to the semiconductor substrate by using the sidewalls as a mask and thereby forming a stepped portion to be covered up with the floating gate electrode in a region of the semiconductor substrate to be formed with the floating gate electrode. The arrangement increases the efficiency with which electrons are implanted into the floating gate electrode.
In the first or second method for fabricating a nonvolatile semiconductor memory device, the tunnel-insulating-film forming step preferably includes the step of forming the third insulating film also on the protective insulating film.
A third method for fabricating a nonvolatile semiconductor memory device, which is for attaining the first object of the present invention, comprises: a control-gate-electrode forming step of forming a first insulating film on a semiconductor substrate, patterning a conductor film formed on the first insulating film, and thereby forming a control gate electrode from the conductor film; a second-insulating-film depositing step of depositing a second insulating film over the entire surface of the semiconductor substrate including the control gate electrode; a protective-insulating-film forming step of selectively removing the second insulating film so as to leave a portion of the second insulating film located on one of side surfaces of the control gate electrode and thereby forming, from the second insulating film, a protective insulating film for protecting the one of the side surfaces of the control gate electrode; a gate-insulating-film forming step of selectively removing the first insulating film so as to leave a portion of the first insulating film underlying the control gate electrode and thereby forming a gate insulating film from the first insulating film; a tunnel-insulating-film forming step of forming, on the semiconductor substrate, a third insulating film serving as a tunnel insulating film; a floating-gate-electrode forming step of forming by self alignment a floating gate electrode capacitively coupled to the side surface of the control gate electrode with the protective insulating film interposed therebetween and opposed to the semiconductor substrate with the tunnel insulating film interposed therebetween; and a source/drain forming step of implanting an impurity into the semiconductor substrate by using the control gate electrode and the floating gate electrode as a mask and thereby forming a source region and a drain region in the semiconductor substrate.
In accordance with the third method for fabricating a nonvolatile semiconductor memory device, one of the side surfaces of the control gate electrode is covered with the protective insulating film also serving as the capacitance insulating film when the floating gate electrode capacitively coupled to the side surface of the control gate electrode with the protective insulating film interposed therebetween and opposed to the semiconductor substrate with the tunnel insulating film interposed therebetween is formed by self alignment. The arrangement reduces damage caused by etching to the control gate electrode and ensures the formation of a memory cell in the nonvolatile semiconductor memory device.
A fourth method for fabricating a nonvolatile semiconductor memory device, which is for attaining the first object of the present invention, comprises: a control-gate-electrode forming step of forming a first insulating film on a semiconductor substrate, patterning a conductor film formed on the first insulating film, and thereby forming a control gate electrode from the conductor film; a second-insulating-film depositing step of depositing a second insulating film over the entire surface of the semiconductor substrate including the control gate electrode; a sidewall forming step of forming sidewalls over the first insulating film and on portions of the second insulating film located on side surfaces of the control gate electrode; a protective-insulating-film forming step of performing etching with respect to the first and second insulating films by using the sidewalls and the control gate electrode as a mask and thereby forming, from the second insulating film, a protective insulating film for protecting the control gate electrode on each of the side surfaces of the control gate electrode, while forming, from the first insulating film, a gate insulating film under the control gate electrode; a protective-insulating-film removing step of removing the sidewalls and then selectively removing the protective insulating film so as to leave a portion of the protective insulating film located on one of the side surfaces of the control gate electrode; a tunnel-insulating-film forming step of forming, in a region in which the semiconductor substrate is exposed, a third insulating film serving as a tunnel insulating film; a floating-gate-electrode forming step of forming by self alignment a floating gate electrode capacitively coupled to the side surface of the control gate electrode with the protective insulating film interposed therebetween and opposed to the semiconductor substrate with the tunnel insulating film interposed therebetween; and a source/drain forming step of implanting an impurity into the semiconductor substrate by using the control gate electrode and the floating gate electrode as a mask and thereby forming a source region and a drain region in the semiconductor substrate.
In accordance with the fourth method for fabricating a nonvolatile semiconductor memory device, one of the side surfaces of the control gate electrode is covered with the protective insulating film also serving as the capacitance insulating film when the floating gate electrode capacitively coupled to the side surface of the control gate electrode with the protective insulating film interposed therebetween and opposed to the semiconductor substrate with the tunnel insulating film interposed therebetween is formed by self alignment. The arrangement reduces damage caused by etching to the control gate electrode and ensures the formation of a memory cell in the nonvolatile semiconductor memory device.
In the fourth method for fabricating a nonvolatile semiconductor memory device, the protective-insulating-film removing step preferably includes the step of removing the sidewalls and then selectively removing respective portions of the protective insulating film covered with bottom surfaces of the sidewalls.
In this case, the protective-insulating-film removing step preferably includes the step of selectively removing the respective portions of the protective insulating film covered with the bottom surfaces of the sidewalls and then selectively removing respective portions of the gate insulating film covered with the bottom surfaces of the sidewalls.
Preferably, the third or fourth method for fabricating a nonvolatile semiconductor memory device further comprises, between the protective-insulating-film forming step and the protective-insulating-film removing step, the step of: performing etching with respect to the semiconductor substrate by using the sidewalls as a mask and thereby forming a stepped portion to be covered up with the floating gate electrode in a region of the semiconductor substrate to be formed with the floating gate electrode.
In the third or fourth method for fabricating a nonvolatile semiconductor memory device, the tunnel-insulating-film forming step preferably includes the step of forming the third insulating film also on the protective insulating film.
Preferably, the third or fourth method for fabricating a nonvolatile semiconductor memory device further comprises, between the control-gate-electrode forming step and the second-insulating-film depositing step, the step of: introducing hydrogen and oxygen into a space over the heated semiconductor substrate, generating water vapor from the introduced hydrogen and oxygen over the semiconductor substrate, and thereby forming an insulating film on each of side portions of the control gate electrode.
In this case, the protective-insulating-film forming step preferably includes forming the protective insulating film by stacking a plurality of insulating films having different compositions.
In the third or fourth method for fabricating a nonvolatile semiconductor memory device, the tunnel-insulating-film forming step preferably includes the step of introducing hydrogen and oxygen into a space over the heated semiconductor substrate, generating water vapor from the introduced hydrogen and oxygen over the semiconductor substrate, and thereby forming the tunnel insulating film, while forming an insulating film having a composition different from a composition of the protective insulating film on a surface of the protective insulating film.
A fifth method for fabricating a nonvolatile semiconductor memory device, which is for attaining the first object of the present invention, comprises: a control-gate-electrode forming step of forming a first insulating film on a semiconductor substrate, patterning a conductor film formed on the first insulating film, and thereby forming a control gate electrode from the conductor film; a second-insulating-film depositing step of depositing a second insulating film over the entire surface of the semiconductor substrate including the control gate electrode; a protective-insulating-film forming step of selectively removing the second insulating film so as to leave a portion of the second insulating film located on that one of the side surfaces of the control gate electrode opposite to the side surface to be formed with a floating gate electrode and thereby forming, from the second insulating film, a protective insulating film for protecting the control gate electrode; a gate-insulating-film forming step of selectively removing the first insulating film so as to remove a portion of the first insulating film underlying the control gate electrode and thereby forming a gate insulating film from the first insulating film; a capacitance-insulating-film forming step of forming a capacitance insulating film on that one of the side surfaces of the control gate electrode to be formed with the floating gate electrode; a tunnel-insulating-film forming step of forming a tunnel insulating film on the semiconductor substrate; a floating-gate-electrode forming step of forming by self alignment the floating gate electrode capacitively coupled to the side surface of the control gate electrode with the capacitance insulating film interposed therebetween and opposed to the semiconductor substrate with the tunnel insulating film interposed therebetween; and a source/drain forming step of implanting an impurity into the semiconductor substrate by using the control gate electrode and the floating gate electrode as a mask and thereby forming a source region and a drain region in the semiconductor substrate.
In accordance with the fifth method for fabricating a nonvolatile semiconductor memory device, the side surface of the control gate electrode opposite to the floating gate electrode is covered with the protective insulating film when the floating gate electrode capacitively coupled to the side surface of the control gate electrode with the capacitance insulating film interposed therebetween and opposed to the semiconductor substrate with the tunnel insulating film interposed therebetween is formed by self alignment. The arrangement prevents damage caused by etching to the control gate electrode and ensures the formation of a memory cell in the nonvolatile semiconductor memory device.
A sixth method for fabricating a nonvolatile semiconductor memory device, which is for attaining the first object of the present invention, comprises: a control-gate-electrode forming step of forming a first insulating film on a semiconductor substrate, patterning a conductor film formed on the first insulating film, and thereby forming a control gate electrode from the conductor film; a second-insulating-film depositing step of depositing a second insulating film over the entire surface of the semiconductor substrate including the control gate electrode; a sidewall forming step of forming sidewalls over the first insulating film and on portions of the second insulating film located on side surfaces of the control gate electrode; a protective-insulating-film forming step of performing etching with respect to the first and second insulating films by using the sidewalls and the control gate electrode as a mask and thereby forming, from the second insulating film, a protective insulating film for protecting the control gate electrode on each of the side surfaces of the control gate electrode, while forming, from the first insulating film, a gate insulating film under the control gate electrode; a protective-insulating-film removing step of removing the sidewalls and then selectively removing a portion of the protective insulating film located on that one of the side surfaces of the control gate electrode to be formed with a floating gate electrode; a capacitance-insulating-film forming step of forming a capacitance insulating film on the side surface of the control gate electrode to be formed with the floating gate electrode; a tunnel-insulating-film forming step of forming a tunnel insulating film in a region in which the semiconductor substrate is exposed; a floating-gate-electrode forming step of forming by self alignment the floating gate electrode capacitively coupled to the side surface of the control gate electrode with the capacitance insulating film interposed therebetween and opposed to the semiconductor substrate with the tunnel insulating film interposed therebetween; and a source/drain forming step of implanting an impurity into the semiconductor substrate by using the control gate electrode and the floating gate electrode as a mask and thereby forming a source region and a drain region in the semiconductor substrate.
In accordance with the sixth method for fabricating a nonvolatile semiconductor memory device, the side surface of the control gate electrode opposite to the floating gate electrode is covered with the protective insulating film when the floating gate electrode capacitively coupled to the side surface of the control gate electrode with the capacitance insulating film interposed therebetween and opposed to the semiconductor substrate with the tunnel insulating film interposed therebetween is formed by self alignment. The arrangement reduces damage caused by etching to the control gate electrode and ensures the formation of a memory cell in the nonvolatile semiconductor memory device.
In the sixth method for fabricating a nonvolatile semiconductor memory device, the protective-insulating-film removing step preferably includes the step of removing the sidewalls and then selectively removing respective portions of the protective insulating film covered with bottom surfaces of the sidewalls.
In this case, the protective-insulating-film removing step preferably includes the step of selectively removing the respective portions of the protective insulating film covered with the bottom surfaces of the sidewalls and then selectively removing respective portions of the gate insulating film covered with the bottom surfaces of the sidewalls.
Preferably, the sixth method for fabricating a nonvolatile semiconductor memory device further comprises, between the protective-insulating-film forming step and the protective-insulating-film removing step, the step of: performing etching with respect to the semiconductor substrate by using the sidewalls as a mask and thereby forming a stepped portion to be covered up with the floating gate electrode in a region of the semiconductor substrate to be formed with the floating gate electrode.
In the fifth or sixth method for fabricating a nonvolatile semiconductor memory device, the capacitance-insulating-film forming step and the tunnel-insulating-film forming step are preferably composed of identical steps proceeding concurrently.
In the fifth or sixth method for fabricating a nonvolatile semiconductor memory device, the capacitance-insulating-film forming step or the tunnel-insulating-film forming step preferably includes the step of introducing hydrogen and oxygen into a space over the heated semiconductor substrate, generating water vapor from the introduced hydrogen and oxygen over the semiconductor substrate, and thereby forming the capacitance insulating film or the tunnel insulating film.
In each of the first to sixth methods for fabricating a nonvolatile semiconductor memory device, the second insulating film is preferably a multilayer structure composed of a plurality of stacked insulating films having different compositions.
To attain the second object, in each of the first to sixth methods for fabricating a nonvolatile semiconductor memory device, the semiconductor substrate preferably has a memory circuit formation region including the source region and the drain region and a peripheral circuit formation region to be formed with a peripheral circuit containing a field-effect transistor for generating and outputting a drive signal to the control gate electrode, the floating gate electrode, the source region, or the drain region, the method further comprising the step of: forming the field-effect transistor in the peripheral circuit formation region after forming the source region and the drain region in the memory circuit formation region.
The arrangement prevents the memory cell of the present invention from affecting the operating characteristics of a field-effect transistor composing the peripheral circuit and thereby implements a nonvolatile semiconductor memory device having desired characteristics.
In this case, the step of forming the control gate electrode in the memory circuit formation region preferably includes the step of forming also a conductor film for forming a gate electrode of the field-effect transistor simultaneously with the formation of the conductor film on the first insulating film. Although the step of completing a field-effect transistor in the peripheral circuit is performed subsequently to the step of producing a memory cell, the conductor film on the first insulating film is formed simultaneously with the formation of the conductor film for forming the gate electrode in the memory circuit formation region. Accordingly, the arrangement omits the step of forming the conductor film for the field-effect transistor without affecting the operating characteristics of the field-effect transistor and thereby reduces the number of process steps.
In this case, the step of forming the control gate electrode in the memory circuit formation region preferably includes the step of patterning also a conductor film for forming a gate electrode of the field-effect transistor simultaneously with the patterning of the conductor film. The arrangement omits the patterning step for the gate electrode of a field-effect transistor without affecting the operating characteristics of the field-effect transistor and thereby reduces the number of process steps.